[SDL] Slowdowns....Speedups!

Gary Scillian scillian at home.com
Tue Aug 3 18:55:59 PDT 1999


brn wrote:
> 
> > > How big is the l1 cache?
> > It's usually pretty small, e.g. 128-512K
> > I'm not actually sure if I am thinking of the L1 or L2 cache.
> > I think the L1 cache is much smaller than that.
> 
> That's the L2 cache.. I just remember the Pentium L1 cache was 32 bytes.
> ah, the good old times where people wrote texture mapping algorithms that
> would try to fit as much as possible in a 32 byte cache :)
> 
> (see for example my tunnel3d demo in OpenPTC :)
> 
> c.

There's some confusion here, I think...

The original Pentium had separate data and instruction L1 caches,
two-way 8KB each; Pentium with MMX doubled this to 16KB each, four-way. 
I believe PII and PPro had the same, and I think PIII has doubled this
again.

Rumor has it that the Celeron 128 is way cool since it has a 128K L2
cache that runs at full core clock speed, making it essentially a huge
(by Intel standards) L1 cache.  This was to make up for not having any
L2 cache at all in the original Celeron.

Most Pentium-class machines I've seen have at least 256K of L2 and 512K
is pretty common.

Each cache line is 32 bytes; maybe that's the 32 you're remembering...

-- 

Gary Scillian  scillian at home.com
"There's a seeker born every minute." - Firesign Theatre



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